1. Field of the Invention
The present invention generally relates to apparatus and methods for testing transmission equipment and a self-test method and more particularly, to apparatus and methods for testing any paths inside transmission equipment and testing paths between the transmission equipment and other transmission equipment, and a self-test method for testing the apparatus mentioned above.
In further detail, this invention concerns apparatus and methods for supervising inside the transmission equipment, which include a function for immediately determining a fault point when trouble occurs in a circuit inside the equipment itself, and also a function for the apparatus supervising itself when no supervision of the transmission equipment is carried out.
Generally, in developing the transmission equipment, previous tests of the transmission equipment are carried out before the transmission equipment is in service. And after service begins, there is a need for determining fault points in troubled equipment, testing the transmission paths inside the equipment itself by means of a self-test apparatus located inside the equipment, and testing the transmission paths between equipment.
2. Description of the Prior Art
FIG. 1 shows a configuration of a conventional test circuit. This circuit comprises a test-pattern generation circuit 100 and a test-pattern check circuit 200.
This test-pattern check circuit 200 includes a first signal selection circuit 210, a second signal selection circuit 221, a reference-pattern generation circuit 224, an exclusive-or circuit 223, a synchronization detection circuit 230, an error counter 240, and a system-clock switching circuit 250. The test-pattern generation circuit 100 has the same configuration as the reference-pattern generation circuit 224, which is configured with an n-stage flip-flop circuit. Each of the test-pattern generation circuit 100 and the reference-pattern generation circuit 224 generates a pseudo-random noise (PN) pattern according to a clock signal supplied through the system-clock switching circuit 250 in the test-pattern check circuit 200. However, in the reference-pattern generation circuit 224, a feedback signal line which is a part of the PN generation mechanism is shown as "signal h", while in the test-pattern generation circuit 100, the feedback signal line is included inside the block 100 and is not illustrated. Therefore, in the reference-pattern generation circuit 224, the second signal selection circuit 221 is inserted in the feedback loop of the PN generation circuit.
The exclusive-or circuit 223 compares a PN pattern in a drop signal z coming from transmission equipment with the reference PN pattern from the reference-pattern generation circuit 224. However, when the self-test is carried out, the exclusive-or circuit 223 compares the PN pattern generated in the test-pattern generation circuit 100 with the reference PN pattern from the reference-pattern generation circuit 224, and determines whether the PN pattern from the test-pattern generation circuit 100 is correct or not. Namely, when the signal pattern coming from the test-pattern generation circuit 100 is identified with the signal pattern coming from the reference-pattern generation circuit 224, the test circuit is recognized as being in a normal condition, and when not being thus identified, the test circuit is recognized as being in a troubled condition in which any fault may be occurring. For example, in the exclusive-or circuit 223, when both the input signal patterns are identical, the circuit supplies a pattern "00000000", whereas when the input signal patterns are not identical, the circuit supplies, for example, a pattern "011100101" including error bits "1". The output of the exclusive-or circuit 223 is applied to the synchronization detection circuit 230. In the synchronization detection circuit 230, the synchronization means that a frame format (for example, 511 bits for 9 stages) repeated on the PN pattern from the test-pattern generation circuit 100 or the transmission equipment is synchronized to that repeated on the PN pattern from the reference-pattern generation circuit 224. Therefore, if a given number of bits "0" is sequentially accepted from the exclusive-or circuit 223, it is decided that synchronization is established. On the other hand, if the sequential bit pattern of "0" for a given number is not obtained, it is decided that the two patterns are out of synchronization.
The first signal selection circuit 210 selects a signal y for the self-test, coupled to a port a, or a drop signal z coupled to a port b, according to a selection signal s1. In the second signal selection circuit 221, if a synchronization detection signal s2 indicates an asynchronous state of the two patterns into the exclusive-or circuit 223, the signal from the first signal selection circuit 210, coupled to a port b, is selected. The selected signal is sent to a delay circuit 222 where the delay time corresponds to that of the reference-pattern generation circuit 224, and is also sent to the reference-pattern generation circuit 224 for setting initial data for the PN generation. And once the synchronization detection signal s2 indicates a synchronous state, a signal h from the reference-pattern generation circuit 224, coupled to a port a, is selected to supply the PN pattern synchronizing with the output of the delay circuit 222 at least the initial some bits. Then, the actual transmission test or self test starts.
In the error counter 240, during a time that the synchronization detection circuit 230 recognizes that synchronization is being established, namely during the transmission test or self test, a synchronous-state signal m is applied from the synchronization detection circuit 230 to the error counter 240, and a number of errors existing in signal ER produced from the exclusive-or circuit 223 is counted.
Next, a description will be given of the operating process of the test circuit shown in FIG. 1.
First, a description will be given of the selection signal used in the test circuit, referenced in FIG. 2. For the case of the self test, the selection signal s1 of the test type is set to "0", while for the case of the normal test, s1 is set to "1". A counter control signal, designated "d", controls a reset-on/off of the count operation of the error counter 240, where the control signal is set to "1" for the reset-off, and is set to "0" for the reset-on. In regard to the synchronization detection signal s2 from the synchronization detection circuit 230, when the synchronous state is determined by the synchronization detection circuit 230, the s2 is set to "0", whereas when the asynchronous state is determined, the s2 is set to "1".
The operation of the conventional test circuit shown in FIG. 1 will be described as follows. FIG. 3 shows a flowchart in relation to the operation of the conventional test circuit.
If the normal test which tests the transmission equipment is selected (step 100), the drop signal z from the transmission equipment is selected in the first signal selection circuit 210 by the selection signal s1 of "1" (step 101), and subsequently the error counter 240 is reset-off by the counter control signal (step 102). Next, the selected drop signal z is applied to the second signal selection circuit 221 and to the delay circuit 222. In the second signal selection circuit 221, first the drop signal z from the first signal selection circuit 210 is selected to send its signal to the reference-pattern generation circuit 224 (step 103). In the reference-pattern generation circuit 224, the drop signal z is sequentially shifted through the n stages of flip-flops which construct the PN generation circuit, while the drop signal z into the delay circuit 222 is also sequentially shifted through n stages of flip-flops which construct the delay circuit having the same delay time as that of the reference-pattern generation circuit 224. Therefore, the output of the reference-pattern generation circuit 224 may be synchronized to the output of the delay circuit 222, and this synchronization may be detected in the synchronization detection circuit 230 through the exclusive-or circuit 223 (step 104 and step 105).
At this time, in the reference-pattern generation circuit 224, each value of the n stages of flip-flops may be the initial value of the PN generation circuit at the time when the second signal selection circuit 221 selects the port a to establish the loop of the PN generation. When the synchronization of the two drop signals from the different paths is detected in the synchronization detection circuit 230, the synchronization detection circuit 230 supplies the synchronization detection signal s2 which indicates, in this case, the synchronous state to the second signal selection circuit 221. Therefore, after the second signal selection circuit 221 selects the port a to establish the PN generation loop in response to the synchronization detection signal s2 (step 106), the drop signal z from the delay circuit 222 is compared with the PN pattern from the reference-pattern generation circuit 224, in which the two signals are in a synchronous state during as least the initial some bits. In this way, the transmission test of the drop signal z through the transmission equipment starts to be carried out by comparing the signal z with the PN pattern generated in the test-pattern check circuit 200.
During the test, the comparison result is applied not only to the synchronization detection circuit 230 as the signal c but also to the error counter 240 as the signal ER. And, at the same time when the synchronization of the two signals into the exclusive-or circuit 223 is detected, the synchronous state signal m which may be the synchronization detection signal is applied to the error counter 240 to enable the counter to begin operation. The error counter 240 then starts to count the error bits existing in the signal ER (step 107). In the flowchart shown in FIG. 3, after the count operation (the step 107), the step 104 is returned to through step 108 and step 109 after each bit operation. If there is a large number of errors in the drop signal z, the error counter 240 overflows (YES of the step 108), and subsequently sends an overflow signal e to a display device 290. In the display device 290, the occurrence of the error state is displayed (step 111).
When the test is finished by termination of the error count (YES of the step 109), the error counter control signal is switched from "1" to "0" (step 110) to reset the error counter 240, and subsequently, the operation proceeds to the self-test procedure.
Next, the operation of the self test in the test circuit will be discussed in the following. The operation of the self test is almost the same as that of the normal test. First, the synchronization between the PN pattern from the test-pattern generation circuit 100 and the PN pattern to be generated in the reference-pattern generation circuit 224 is established. Next, the two PN patterns are compared.
For the self test, the selection signal s1 of "0", which indicates the self test, is applied to the first signal selection circuit 210 in the test-pattern check circuit 200 (step 201). Therefore, in the first signal selection circuit 210, the PN pattern y from the test-pattern generation circuit 100, coupled to the port a, is selected and is applied to the port b of the second signal selection circuit 221 and the exclusive-or circuit 223. At first, the two signals applied to the exclusive-or circuit 223, namely the signal from the reference-pattern generation circuit 224 and the PN pattern coming from the test-pattern generation circuit 100, are not in a synchronous state. Therefore, the synchronization detection circuit 230 produces the synchronization detection signal s2 of "1" so as to select the PN pattern coupled to the port b in the second signal selection circuit 221 (step 203). Thus, the PN pattern coming from the test-pattern generation circuit 100 passes into the reference-pattern generation circuit 224 and sets the initial values of the PN pattern to be generated in the reference-pattern generation circuit 224.
When the PN pattern from the first signal selection circuit 210 and the PN pattern through the reference-pattern generation circuit 224 are in the synchronous state, the synchronization detection circuit 230 produces the synchronization detection signal s2 of "0" (step 205) so as to select the port a of the second signal selection circuit 221 (step 206). In the reference-pattern generation circuit 224, the PN pattern is generated by the feedback loop being formed, and is applied to the exclusive-or circuit 223. In this way, in the exclusive-or circuit 223, the PN pattern selected in the first signal selection circuit 210 is compared with the PN pattern generated in the reference-pattern generation circuit 224.
At this time, the exclusive-or circuit 223 carries out the exclusive-or logical operation with the above two signal patterns. The result of the exclusive-or logical operation is applied not only to the synchronization detection circuit 230 as the signal c but also to the error counter 240 as the signal ER. In the synchronization detection circuit 230, when the synchronization is detected, the synchronous state signal m is produced to the error counter 240 to enable the count operation. Therefore, in response to the signal m which indicates the synchronous state, the error counter 240 starts to count error bits existing in the signal ER (step 207). And procedures from step 204 to step 209 are repeated until the test is finished as long as the synchronization is continued.
If any fault occurs in the test-pattern generation circuit 100 or the reference-pattern generation circuit 224, the signal ER from the exclusive-or circuit 223 may include errors which are to be counted in the error counter 240. When the count number of the error counter 240 exceeds a given number of errors, the over-flow signal e representing the count number is sent to the display device 290 (YES of step 208) which displays the error conditions according to the count number of the over-flow signal e (step 211). This display indicates that trouble is occurring in the test circuit.
When the test is finished (YES of the step 209), the error counter control signal is switched from "1" to "0" (step 210) to reset the error counter 240.
Furthermore, this test circuit is constructed using a redundancy system clock, in which a system-clock selector 250 may select either a clock of line 0 or a clock of line 1. A clock selection signal g is applied to the system-clock selector 250 from an external device (not shown) so as to supply a proper clock to the test-pattern generation circuit 100 and the reference-pattern generation circuit 224. These circuits are respectively operative by synchronizing to the system clock.
In the conventional construction mentioned above, if during the test any trouble occurs in the clock which is currently being selected as the system clock, by the order of the selection signal g the system-clock selector 250 is controlled to switch to the other proper clock as the system clock. However, in general it is hard to carry out the switching without any turbulence of the clock, so that in the switching operation the system clock from the system-clock selector 250 is imposed to have the switching turbulence. In addition, the two clock sources coupled to the system-clock selector 250 are independently operative and the phases of the clocks are not in synchronization with each other. Further, the switching timing in the system-clock selector 250 is not also synchronized to the two clocks. Therefore, if the switching timing and a falling edge or a rising edge of each of two signals are almost close each other, the selected system clock is imposed to have a non-uniform period. However, in such a test apparatus, a normal clock and an inverted clock are generally used. Therefore, the non-uniform period in the clock causes the clocking timing to be shifted. The turbulence and the non-uniform period cause the incomplete clock pulses, by which all circuits receiving such a system clock may not be simultaneously clocked. Therefore, the switching turbulence and the non-uniform period may cause asynchronous clocking of all of circuits included in the test circuit. And thus, the synchronization between the two signals into the exclusive-or circuit 223 may be out, the above causing the error counter to overflow, in which case an alarm for the fault of the transmission equipment is produced. Therefore, false information indicating transmission equipment trouble may be displayed although no trouble has occurred in the transmission equipment. There is thus the problem that the switching of the system clock in the system-clock redundancy system interferes with a stable transmission test.